While some leakage power reduction techniques require modification of the process technology, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter and determine the effects of dual threshold voltage over five leakage power savings techniques: Sleep Transistor, Sleepy Stack Transistor, Sleep Keeper, LECTOR and Our Proposed technique (VSECURE).Two Input NAND gate is consider as a base case for assessment of above mentioned technique using Tanner EDA tool. In this research work effect of dual threshold voltage over static power dissipation, dynamic power dissipation and on propagation delay is experimentally observe using predictive technology 90nm models.
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